The TP2522 low-threshold, Enhancement – mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices.
P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ISSUE 2 – MARCH 94 FEATURES * 60 Volt V DS *R DS(on) =5? ABSOLUTE MAXIMUM RATINGS. PARAMETER SYMBOL VALUE UNIT Drain-Source Voltage V DS-60 V Continuous Drain Current at T amb=25°C I D-280 mA Pulsed Drain Current I DM-4 A Gate Source Voltage V GS ± 20 V Power Dissipation at T amb=25°C P tot 700 mW, P-Channel Enhancement-Mode Vertical DMOS FETs Low Threshold DMOS Technology These low threshold enhancement-mode (normally-off) transis-tors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors, P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ISSUE 2 – MARCH 94 FEATURES * 100 Volt V DS *R DS(on) =8? ABSOLUTE MAXIMUM RATINGS. PARAMETER SYMBOL VALUE UNIT Drain-Source Voltage V DS-100 V Continuous Drain Current at T amb=25°C I D-230 mA Pulsed Drain Current I DM-3 A Gate Source Voltage V GS ± 20 V Power Dissipation at T amb=25°C P tot 700 mW, P-Channel Enhancement – Mode Vertical DMOS FETs Features Low threshold — -2.4 V max High input impedance Low input capacitance — 85pF typical Fast switching speeds Low on resistance Free from secondary breakdown Low input and output leakage Complementary N- and P.
ZVP2106A P-channel enhancement mode vertical DMOS FET …
ZVP2106A P-channel enhancement mode vertical DMOS FET …
ZVP2106A P-channel enhancement mode vertical DMOS FET …
P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ISSUE 2 Œ MARCH 94 FEATURES * 100 Volt VDS *RDS(on)=20? ABSOLUTE MAXIMUM RATINGS. PARAMETER SYMBOL VALUE UNIT Drain-Source Voltage VDS-100 V Continuous Drain Current at Tamb=25°C ID-140 mA Pulsed Drain Current IDM-1.2 A Gate Source Voltage VGS ± 20 V Power Dissipation at Tamb=25°C Ptot 625 mW, P-Channel Enhancement – Mode Vertical DMOS FETs Absolute Maximum Ratings Drain-to-Source Voltage BV DSS Drain-to-Gate Voltage BV DGS Gate-to-Source Voltage ± 20V Operating and Storage Temperature -55°C to +150°C Soldering Temperature* 300°C * Distance of 1.6 mm from case for 10 seconds. Low Threshold Ordering Information BV, ZVP2120A datasheet, ZVP2120A datasheets, ZVP2120A pdf, ZVP2120A circuit : ZETEX – P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ,alldatasheet, datasheet, Datasheet search site for Electronic Components and Semiconductors, integrated.
because of low on-state resistance compared to P-channel devices. An N-channel depletion- mode Power MOSFET differs from the enhancement – mode in that it is normally ON at 0V gate bias and requires a negative gate bias to block current [2]. Vertical DMOS Structure A simplified vertical DMOS Power MOSFET with four layers of n+pn-n+ structure is …
For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.VP0808Advanced DMOS TechnologyThese enhancement – mode (normally-off) transistors utilize avertical DMOS structure and Supertex’s well-proven silicon-gate datasheet search, datasheets, Datasheet …
